Jeffrey S Vetter

Group Leader - Future Technologies Group

Jeffrey S. Vetter, Ph.D., is a Distinguished R&D Staff Member, and the founding group leader of the Future Technologies Group in the Computer Science and Mathematics Division of Oak Ridge National Laboratory. Vetter also holds a joint appointment at the Electrical Engineering and Computer Science Department of the University of Tennessee-Knoxville. From 2005 through 2015, Vetter held a Joint position at Georgia Institute of Technology, where, from 2009 to 2015, he was the Principal Investigator of the NSF Track 2D Experimental Computing XSEDE Facility, named Keeneland, for large scale heterogeneous computing using graphics processors, and the Director of the NVIDIA CUDA Center of Excellence.

Vetter earned his Ph.D. in Computer Science from the Georgia Institute of Technology. He joined ORNL in 2003, after stints as a computer scientist and project leader at Lawrence Livermore National Laboratory, and postdoctoral researcher at the University of Illinois at Urbana-Champaign. The coherent thread through his research is developing rich architectures and software systems that solve important, real-world high-performance computing problems. He has been investigating the effectiveness of next-generation architectures, such as non-volatile memory systems, massively multithreaded processors, and heterogeneous processors such as graphics processors and field-programmable gate arrays (FPGAs), for key applications. His recent books, entitled "Contemporary High Performance Computing: From Petascale toward Exascale (Vols. 1 and 2)," survey the international landscape of HPC

Vetter is a Fellow of the IEEE, and a Distinguished Scientist Member of the ACM. In 2018, Vetter was awarded the ORNL Director's Award for Outstanding Individual Accomplishment in Science and Technology. As part of an interdisciplinary team from Georgia Tech, NYU, and ORNL, Vetter was awarded the Gordon Bell Prize in 2010. Also, his work has won awards at major venues: Best Paper Awards at the International Parallel and Distributed Processing Symposium (IPDPS), EuroPar and the 2018 AsHES Workshop, Best Student Paper Finalist at SC14, Best Presentation at EASC 2015, and Best Paper Finalist at the IEEE HPEC Conference. In 2015, Vetter served as the Technical Program Chair of SC15 (SC15 Breaks Exhibits and Attendance Records While in Austin).