March 2025

Conference Paper

QECC-Synth: A Layout Synthesizer for Quantum Error Correction Codes on Sparse Architectures

By:
Yin, Keyi; Zhang, Hezi; Fang, Xiang; Shi, Yunong; Humble, Travis S; Li, Ang; Ding, Yufei
Page Number:
876-890
Volume:
1
Book Title:
ASPLOS '25: Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems
Publication Date:
March 2025
Publisher Location:
Association for Computing Machinery, New York, United States of America
Conference Name:
30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2025)
Conference Location:
Rotterdam, Netherlands
Conference Sponsor:
ACM SIGPLAN
View DOI Listing:
https://doi.org/10.1145/3669940.3707236

Abstract

Quantum Error Correction (QEC) codes are essential for achieving fault-tolerant quantum computing (FTQC). However, their implementation faces significant challenges due to disparity between required dense qubit connectivity and sparse hardware architectures. Current approaches often either underutilize QEC circuit features or focus on manual designs tailored to specific codes and architectures, limiting their capability and generality. In response, we introduce QECC-Synth, an automated compiler for QEC code implementation that addresses these challenges. We leverage the ancilla bridge technique tailored to the requirements of QEC circuits and introduces a systematic classification of its design space flexibilities. We then formalize this problem using the MaxSAT framework to optimize these flexibilities. Evaluation shows that our method significantly outperforms existing methods while demonstrating broader applicability across diverse QEC codes and hardware architectures.


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