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In-Depth Optimization with the OpenACC-to-FPGA Framework on an Arria 10 FPGA...

by Jacob B Lambert, Seyong Lee, Jeffrey S Vetter, Allen Malony
Publication Type
Conference Paper
Book Title
2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
Publication Date
Page Numbers
460 to 470
Publisher Location
New Orleans, Louisiana, United States of America
Conference Name
The Nineth International Workshop on Accelerators and Hybrid Exascale Systems
Conference Location
New Orleans, Louisiana, United States of America
Conference Sponsor
Conference Date

The reconfigurable computing paradigm that uses field programmable gate arrays (FPGAs) has received renewed interest in the high-performance computing field due to FPGAs' unique combination of performance and energy efficiency. However, difficulties in programming and optimizing FPGAs have prevented them from being widely accepted as general-purpose computing devices. In accelerator-based heterogeneous computing, portability across diverse heterogeneous devices is also an important issue, but the unique architectural features in FPGAs make this difficult to achieve. To address these issues, a directive-based, high-level FPGA programming and optimization framework was previously developed. In this work, developed optimizations were combined holistically using the directive-based approach to show that each individual benchmark requires a unique set of optimizations to maximize performance. The relationships between FPGA resource usages and runtime performance were also explored.