Nanoelectronics beyond 2020?

10:00 AM - 11:00 AM
Avik Ghosh, The University of Virginia, Charlottesville
CNMS Seminar
Center for Nanophase Materials Sciences (Building 8610), Room L-183
Email: Xiaoguang Zhang

It is generally believed that the biggest challenge to the continued scaling of semiconductor electronics is the high cost of binary switching. Simulation plays a critical role in deconstructing the physics of emerging devices, as well as guiding material and device design. On the material front, we can use sophisticated electronic structure theory to scan through entire classes of materials to identify promising behavior, such as high magnetic polarization. On the transport front, we have learned a great deal on how electrons flow at atomic scales through a combination of wave like interference and particle like scattering pathways. Our simulation infrastructure can help visualize charge, spin and heat flow through millions of atoms and compute their properties predictably. Through these studies, we have a growing understanding of what digital switches may need to look like in order to operate at very low power. The energy dissipated in today's devices is governed by the number of redundant charges set by interconnect ‘drivability', and the switching energy per unit charge, set by the Landauer thermal limit of kTln2. Accordingly, one way to circumvent these limitations is to design ‘correlated switches', - as in nano-magnetic/ferroelectric logic and spin torque transfer memories (STTRAMs), where many charges or spins lock and switch together for the energy cost of a few. The main challenge here is to create the switching fields in an energy efficient manner. An alternate class is ‘subthermal switches' such as tunnelFETs and mechanical relays where each degree of freedom operates near a phase transition point below the Landauer limit. I will end with the emerging world of 2D chiral materials such as graphene and topological insulators, where the locking of spin/pseudospin with momentum across a pn junction might allow us to engineer a gate tunable transport gap and thus a high speed low power switch using geometry alone.


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