How do you program a 64,000 core single chip CPU?

10:00 AM - 11:00 AM
Andreas Olofsson, Adapteva, Lexington, Massachusetts
Computer Science and Mathematics Division Seminar
Joint Institutie for Computational Sciences (Building 5100), Auditorium (Room 128)
Email: Jay Jay Billings

This talk will review the past, present and (likely) future of processor hardware from a chip designer's perspective and outline the many challenges facing us in making use of parallel hardware. We will demonstrate a sub 2 Watt working silicon product with 64 RISC cores occupying 10mm^2 at 28nm and will show how this architecture can scale to 64,000 RISC cores on a chip by 2018. With so much parallelism now available on a single chip, we need to rethink everything.

Andreas Olofsson (@adapteva) founded Adapteva in 2008 with a mission to build the most efficient processor in the world. Adapteva has so far created four generations of multicore chips, the latest one being a 64-core floating point microprocessor implemented in 28nm that consumes less than 2 Watts. In the fall of 2012, Adapteva launched the Parallella project that aimed at making parallel computing ubiqutous . Prior to starting Adapteva, Andreas worked at Analog Devices for 10 years developing energy efficiency DSPs and mixed signal SOCs like the TigerSHARC DSP. Andreas holds bachelor's degrees in Physics and Electrical Engineering  and a Masters of Electrical Engineering from the University of Pennsylvania.


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