Research
|
|
|
EUVL reaching commercialization, Intel, the founding member of the Extreme Ultraviolet Lithography Limited Liability Corp., has placed an order for the first beta version of a lithography tool based on technology developed at Sandia through a historic labs-industry partnership. An unprecedented $250 million Cooperative Research and Development Agreement in 1997 between the Intel-led consortium and the Virtual National LabSandia, Lawrence Livermore and Lawrence Berkeley national laboratoriesled last year to integration of the first full-field EUVL chip-patterning tool, the Engineering Test Stand, at Sandia. "It's no longer just a VNL technology," says Glenn Kubiak, leader of the Nanoscale Science and Engineering Section at Sandia's California lab site. "It's becoming a truly commercially available technology, with an order from the world's largest exposure tool manufacturer (ASML)." In keeping with this transition from a pre-competitive phase of collaborative research with industry, the VNL is poised to begin a technology maturation phase by offering access to a Resource Development Center (RDC) at the VNL beginning next year. In the RDC, research agreements are anticipated from integrated circuit manufacturers, the EUV group, semiconductor equipment manufacturers such as ASML, and Sematech, the advanced manufacturing and development consortium. Since celebrating completion of the Engineering Test Stand last year, says Kubiak, efforts have focused on making upgrades to enable reliable access to chip companies that will use the tool for process development and learning. Individual companies can practice exposing wafers with circuit patterns using the exposure tool. Equipment manufacturers, meanwhile, will study the tool environment to reduce contamination of the optical system and investigate the EUV light source. EUV patterning, or lithography, is considered an extension of the current approach to reducing and printing circuit patterns on wafers. However, EUV light is more than 10 times shorter in wavelength, requiring the use of reflective image-reduction surfaces and photomasks, since this wavelength would be absorbed by traditional clear lenses. This next-generation approach was undertaken because the chip-making industry faced insurmountable physical limits along its path of doubling the number of transistors that can be packed into a chip every 18 to 24 months, a pace that has driven the business over the past 30 years. Patterning wafers with shorter wavelengths of light enables finer features, and thus, more densely-packed transistors. That translates into better performance, with clock speeds of up to 10 GHz or fastercompared with the best speeds today of 2.4GHz. The beta tool ordered by Intel is expected to be delivered in 2005, and the first commercial chip production with EUVL should take place in 2006-07. ASML anticipates it will be used to image critical layers in integrated circuits with feature sizes below 45 nm. Submitted by DOE's Sandia National Laboratory |
| DOE Pulse Home | Search | Comments |