IEEE Nuclear Science Symposium 1996
A Multi-Channel ADC
for Use in the PHENIX Detector M. S. Emery, S. S. Frank, C. L. Britton, Jr.,
A. L. Wintenberg,
M. L. Simpson, M. N. Ericson, G. R.Young, L. G. Clonts, M. D. Allen
A custom CMOS analog to digital converter was designed and a prototype 8-channel ADC
ASIC was fabricated in a 1.2 mm process. The circuit uses a Wilkinson-type architecture
which is suitable for use in multi-channel applications such as the PHENIX detector. The
ADC design features include a differential positive-ECL input for the high speed clock and
selectable control for 11 or 12-bit conversions making it suitable for use in multiple
PHENIX subsystems. Circuit topologies and ASIC layout specifics, including power
consumption, maximum clock speed, INL, and DNL are discussed. The ADC performed to 11-bit
accuracy.
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